|
|
Single-Chip 16-Port SerDes Gigabit Switch' p. S9 O/ J; I- B$ c
" l. h0 s" r) n0 N) t1 N) v% p. ]
16-port 10/100/1000 Mbps integrated switch
0 A3 A0 W. V! {& L9 ]controller via 1.25G SerDes/SGMII/fiber
H" S" y% ^3 J. ` c( C& V• Embedded 256 KB on-chip packet buffer. O5 @$ R. _: r4 E
• One 10/100/1000 Mbps In-band Management
# q+ z6 S8 X9 c5 ?6 E& V+ h1 XPort (IMP) with GMII/RGMII/RvMII/MII interface
% N3 T( c0 G( Hfor PHY-less connection to a CPU/management' J |' B' I+ y2 N: V
entity (for management purposes only)
; @+ ~8 I' c5 {1 @! G9 d• Integrated address management
6 ?/ ]6 ]1 s+ X7 _5 x3 n2 }' `• Supports up to 4K MAC addresses: H7 @, i+ @& H" ?3 ]' }6 _, L
• Supports jumbo frames up to 9728 bytes.
! y: V& F6 A1 W• Supports EEPROM for low-cost chip configuration: m1 V4 N+ N( V8 r7 V: X. S/ N
• Integrated Motorola® SPI-compatible interface$ i r" A: Y, s4 U' y' ]9 l
• Supports port mirroring
+ n- d7 V4 b% p t f/ O• Port-based VLAN and 4K IEEE 802.1Q tag VLAN
( ]6 h4 j9 G7 ` ^; z% P• Port-, DiffServ-, MAC-, and IEEE 802.1p-based QoS- j8 s" V8 d% B1 V& |* ?
for four queues
0 D6 ~( v3 Z' |6 |• Supports Spanning Tree, Rapid Spanning Tree, and
9 T) p$ \; j2 }- S* bMultiple Spanning Tree protocols (802.1D/1s/1w)
: E' Y: |' i4 Q* d; u- U• Supports IEEE Standard 802.1X port security
2 n& O+ E4 x" c+ l& b• Supports pseudo-PHY MDIO access
' w7 r; T: w+ V$ x• MAC-based trunking with link fail-over4 G+ ?( b4 n- K
• Ethernet-in-the-last-mile (EFM) support: OAM and
- G) q3 h8 Q! S; k, Q) {P3 H0 o3 ]( ?2 W1 x6 R u& @4 ^
• Low-power (2.2W total) 1.2V core/2.5V (SGMII I/
, c& R8 g9 `; q# I+ U: [8 HO)/3.3V (GMII/MII/RvMII) and 2.5V RGMII
5 ^+ n {$ s7 D$ i& j9 I( ~operation with 3.3V I/O tolerance8 h, [ d/ P# j2 G% _: z, ?
• 256-pin FBGA package$ D, M- t4 F6 O- i4 A
BCM5396 Data sheet
* h. s) \; x) j! z# ^1 kRevision History$ w0 U' v# L0 A8 {) L
Revision History
, E& m) e( Z1 r" ~# d1 D! C; b$ @Revision$ P& @8 }. F& {, L
Date$ V! m [# { ^; o+ w
Change description
9 S% U9 z: d) M6 t7 Y' u5396-DS114-R10/4/13 Added/ Q' Y) p" u( e% f/ H7 S
"ethertype based qos on page 29
3 u7 u( ]1 N8 y% _" yUpdated:
: A9 f& P* T4 KFigure 2: Priority packet Mapping Flow, on page 278 ?$ k; F* N2 Z4 `) w8 i |' M
Table 1: Frame Priority Decision Tree Summary on page 30
7 X6 `+ b( ], J* O1 A" V·“ Jumbo frame Support" on page33
: F2 _- p, C8 u2 B4 }% W( CTable 17: Pseudo-PHY Mll Register Definitions on page 72
7 l. e) ?% ~9 v- x: ?2 USerial LED Interface"on page 74
) \; Z2 @/ Q) f0 W/ Y8 A& w6 WTable 43: External PHY Scan Control Register(Page oOh: Address 86h)/ g- Q6 B% m8 M* _
on page 101" g- y$ O+ ~$ W! b0 @
Table 177: Serial lEd Interface Timing, on page 1915 b; L, \- k+ e/ c% i, g/ X
5396-DS113-R 02/07/12 Updated
6 t1 H$ |' t9 S& i) q% z3 r4 DTable 139: Internal Ser Des registers Page descriptions 10h-1Fh, " on
0 w# u, M- {( }8 Z, w7 X) Wpage 145. X; ^4 X* c4 u* C! d" ^. g- h+ p
Table 140: " Internal Ser Des Registers Page 10h-1Fh on page 1451 k L7 w4 y O: V& h
Table 192: New Priority Map Register(Pages 34h: Address oC-OFh,on: _* A% @, W8 M7 H
page 185
. g3 v6 e9 z4 `5396-DS112R06/10/10 Updated:
3 X: L4 }: }4 i) ITable 144: Auto-Negotiation Link Partner ability (page 10h-1Fh1 W: m8 }# {6 `( U- T
Address 0Ah-OBh), on page 1537 S) p5 O8 M. p% ~) ~
PRBS Status Register(Page 10h"1Fh: Address 32h" 33h)"on page 166.
+ L/ Z5 G6 h" m" D' G, m6 n6 N5396-Ds111R08/2609 Updated:3 `; a- B0 A% }0 K$ ^" X n
Section 12: Ordering Information, on page 175
9 M5 |4 d: x; }6 z5 }% I1 X8 x5396-DS110R02/2508 Updated:
- g2 R; q a/ g i! {Signal descriptions on page 54: BIST CLRMEM SEL and SKIP MEMbIS
H x8 }, Q* ^descriptions
) ]$ g: N0 M; E6 FRemoved" Z4 u( S1 o3 O
References to behavior of management frames in unmanaged mode
& s% T# ~9 W: ]5396-DS109R11/13/07 Updated
9 V9 t6 Y* S" e% _Management Frames" on page 24, and"Frame Management on9 Q5 [% ^, D1 D m& o$ d) ]% c
page 32: Corrected terminology relating to the in-band management/ @0 z, O7 M* V" Z5 i
port
% ^/ _' s! ?6 S2 c5 PTable 59, Management Mode registers (Page 02h), on page 81:1 k: X6 O& {+ v" a0 K7 K
Changed definition of bits 7: 6+ ` H! b* ~4 b5 o$ W0 C: |
Added:/ s! r" ^8 Y9 k
In-Band Management port"on page 33 Added note
. l# K9 E8 k$ D( v$ N) {9 QTable 23, Signal Descriptions, on page 53 and "Pin Assignments"on
/ m4 Y' h% u3 ~: e3 v! v& k) Z+ A3 Xpage 58: Added BIST CLRMEM SEL, SKIPMEMBIST, EN EXT CLK, and
: j8 M0 x+ L" x9 q' [- [+ W3 s8 KEXT CLK signals to all signal/pin tables and figures
0 x: I& C$ `) {BROADCOMe& D+ R, g& a8 J# t2 C4 h+ C& \ W
Single-Chip 16-Port SerDes Gigabit Switch) T1 Q! O/ l- E% Y; x7 q& H
October4,2013·5396-DS114-R: k" @, [4 z$ {% h/ Y0 W8 m
Page 3
9 l1 R {7 m4 t1 ?) c, MBROADCOM CONFIDENTIAL
8 r! u/ y+ r8 {# m, H3 ~5 r
+ d) w, ]+ b! n" Q& jBCM5396 Data sheet
( [+ E, _- K6 v: o' y/ W+ oRevision History' n' S/ h) |2 S$ t: t
Revision
( T% R8 O& V$ B9 N0 C8 n) YDate
]) T; D! _1 pChange description
. E2 ]9 ?0 Q2 E7 y( G% r5396-Ds108R06/2507 Updated: Y5 D* e$ }% M( _9 a
In-Band Management Port"on page 33
0 x* q) Y3 s) K6 \, m5 @Table 28, 10/100/1000 Port Control Register(Page o0h: Address 00h-
3 j4 U7 X7 N; V) b) u) DOFh),on page 69. [0 \$ t/ {2 s! W
Table 29, "IMP Port Control Register(Page 00h: Address 10h), on page* H4 k7 \8 Q8 }: e: C% S
69.
& o. a6 `# C( O7 r# g4 TTable 66, Global Management Configuration Register(Page 02h
9 v7 ^( d/ V4 h: m, |; TAddress ooh), on page 86
* ^* t9 H+ ^" v9 M1 j3 x7 zTable 229, Thermal Properties with External heat sink 23 mm. 23 mm
" y' j3 V2 e% i, F15 mm. Blade Fin, on page 180
0 t% G; Y4 ]$ w5 \! @/ \Removed2 l- o. S& ]$ k2 i0 K# |
Memory Test Control Register Page 00h: Address EOh) from page 754 H2 Q% c; j8 B' Q: _& U8 ^. f
5395DS107-R07/126 Updated:
8 n& O' }6 Q7 H# a! g2 o0 aFigure 39, 256-Pin FBGA Package Outline Drawing, on page 181
( w$ ]: `8 d( ^. b; @1 a: l5396-DS106-R05/2406Aded:
' m2 o* a# U1 h8 F0 ATable 154, BER/CRC Error Counter Register(Page 10h" 1Fh: Address 2Eh
7 ?2 }% ~7 f; q6 S2Fh),on page 1285 h& H( i2 Z4 W/ \2 K
Table 155, PRBS Control Register(Page 10h"1Fh: Address 30h "31h)3 Y& m$ f/ g+ a8 f0 s; g* ?
page 128) Q e& d* m' Z" r" @6 A. W8 I- y
Table 156, PRBS Control Register(Page 10h" 1Fh: Address 32h" 33h),, [3 \% T8 \$ M
on page 128" v6 a2 q7 V& o* j$ W0 ~ }
Table 157, Pattern Generator Control Register( Page 10h 1Fh: Address) D/ F' S( o R, N! k1 L+ |
34h"35h),on page 129
5 @7 V i4 A6 P% W1 z# [Table 158, Pattern Generator Control Register(Page 10h 1Fh: Address8 [* w ?# [; d8 h) V
36h" 37h), on page 130& k, k: k1 W+ L7 f) V2 n( C
Table 159, Pattern Generator Control Register(Page 10h" 1Fh: Address2 ?: P: u4 S+ l
36h~37h)," on page130.
$ @: ], [0 ~% h7 J0 A, ITable 160, Force Transmit 1 Register(Page 10h" 1Fh: Address 3Ah5 z+ G. G2 d0 |; p; {
3Bh),on page 130
& i+ L4 |. a/ ?1 LTable 161, Block Address(Pages 10h-1Fh: Address 3Eh"3Fh),on page$ }# |& S, z+ r$ p* [
1317 s5 W* x! U/ ^) C3 W
BROADCOMe
8 [8 w; P# b9 q- {Single-Chip 16-Port SerDes Gigabit Switch7 y" e: O, D& B& ?7 y& s
October4,2013·5396-DS114-R
* w' U4 V/ h" x* f5 `6 _Page 4* u6 ~$ t% v! T" c& x
BROADCOM CONFIDENTIAL7 H1 @6 B9 I5 t; l! `
- f# B8 b2 i+ |7 f) T) B, c* g- xBCM5396 Data sheet
" a8 k1 e! F: tRevision History' s5 U1 @+ q) Y# t3 D; w
Revision8 h0 |$ @6 |* h( l% G
Date
. S( ^" _: z; o: E$ S3 HChange description
- I5 T7 \1 a0 n5 E! o5396-DS105R0419/06 Updated:/ U; y- p2 r `' f
Features list on front cover* @0 H) i( @ @; V% V) T! L6 X
."LED Interfaces" on page 508 b8 y' a3 {' E# e% j8 b
Table 23, "Signal Descriptions on page 53' A" t, [* x" v# V
Table 24, "Pin Assignment(Listed by pin Number) on page 58# J% Q+ C" o% i$ \6 ^7 o
Table 25, "Pin Assignment ( Listed by Signal Name), on page 60
& ?, E" o ]8 d' F) }5 U0 \2 Z· Figure21,“ Pins Top view," on page62.2 a0 H6 s! X; J" R
Table 27, "Control Registers(Page ooh),"on page 67.
' O( l6 S$ ]& s1 N* W c, sLED A, B, C, and d registers to reserved in Table 27, Control registers ~" B* l" e( U" F- ~0 `- W8 [
(Page ooh), on page 67
' }2 b$ y8 L6 u ]Table 65, Strap value Register(Page 01h: Address 70h-73h), " on page7 O* E( X- f& `6 C* z* N1 s5 ^" t* x
85
, i0 m* `, q: Z$ R; UTable 94, " ARL Search Result Register(Page 05h: Address 3Bh-3Eh), on
6 K* p: B+ X: L& O6 x6 @* Ipage 98- z: E- P1 m: x+ D
Table 95,"ARL Search MAC/VID Result Register 1(Page 05h: Address* i) }! k" s6 |, y5 |
40h-47h) , on page 98' m1 x8 H* H7 G0 Z& {
Table 231," Ordering Information on page 182( t; o! i' q, P) \7 F6 k
Removed
3 W4 E) I8 E) R2 U! SLED A, B, C, and d register descriptions from section"Control registers
* k$ n6 p7 y, M+ T \on page 67.
- j5 {9 a" v& ?7 b1 v, A5396-DS104R11/10/05Aded:
. V8 Z# U; _* I% j3 KI-temp package ordering information to Table 223,"Ordering3 O g. ~3 T& m4 O' h& t
Information7 X1 Y0 ~3 p+ K4 h
5396-DS103-R 09/21/05 Updated$ p* A+ C; a; E
The minimum, typical, and maximum for the 2.5v power rail pin in table7 x) \) m! D8 |+ A
208, "Electrical characteristics
5 L. C9 b" ~5 a; z/ U/ B& d8 n9 d5396Ds102R09/1605 Updated:
! P. R6 e" Z. B+ z& G0 ZThe minimum, typical, maximum, and units for the 2. 5v power rail pin in9 n1 Z5 Z( K% t0 w6 r) H" ^
Table 208, Electrical Characteristics
/ H. Q* j" N6 t- j& X Y/ c* IAdded:
& }+ B" v0 I6 G0 z- k' H! I5 q4 |3. 3V power rail (IMP port) pin for IDD symbol in Table 208,"Electrical4 y# ?' b+ f v: o( Y9 n& q& S' \$ d
Characteristics"89 N L! g7 b# N$ }+ g& B% _
BROADCOMe
! ?3 o2 t& v( f5 j& |# j4 PSingle-Chip 16-Port SerDes Gigabit Switch
5 q' C# S3 u: X8 D4 fOctober4,2013·5396-DS114-R% O- T, u5 Q! W- N T
Page 5/ e5 l6 p2 t" z3 B$ l2 x
BROADCOM CONFIDENTIAL# E! Q' W- x }3 O/ X% X
/ o, I/ d# r2 p( WRevision4 q* O6 A& T9 c a* I i" S
Date
" {3 a7 J e# ^& U7 @* |Change Description$ _, f6 P$ v* {- m6 Z! M
5396-DS101-R 09/13/05 Updated( z$ _# F0 @6 D% L8 D1 K# J, M4 H
Figure 16, Serial EEPROM Connection, on page 421 X5 w6 U+ q* W: Q) |3 S- A; [
That the aUto Poll DiS pin is pulled low,
# o* S! c2 F& \( y+ {reset in"MDC/MDIO Interface"on page 4 hot high, during power-on/
: s) b; G+ [: BFigure 17, MDC/MDIO Interface, on page 443 [' h! r5 A9 F& l
When the switch is master-sourcing to When the switch is slave-driven in
/ d }3 U8 z' S9 NMDC/MDIO Interface Register Programming"on page 492 K" P' F2 Y# G+ S) }- v7 I* ]
In Table 23, Signal Descriptions on page 53
; e& S" B5 p3 kDescription for hw fWdG EN; ]* y/ X5 X3 k2 z: L- ?
Type for EXTCLK
) @% T; j+ V* x( L: l- SPages 50h-60h to Reserved in Table 26, Global Page Register Map on0 [3 P. g# k1 M* [7 X
age 64$ O! q: f$ [9 D1 @, f g+ w- j, X
The Description in Table 95, ARL Search Control register(Page 05h
- z9 N4 W" n0 @/ ^Address 30h),on page 98, G9 y" Q% Q- O+ E
The default in Table 169, "Queue N Weight Register(Page 30h: Address I6 c( H$ d) w# j2 k3 Z
81h-84h), "on page 132+ U% x" Q/ k0 F- Z
Table 208, Electrical Characteristics, on page 1587 j8 x: i6 R* A
Added
. W" L6 X( L0 w. ]8 Z- k) G6 ~Page 00 Addr 24H"25H Bit[10: 8] to Table 19, "Serial LED Mode matrix9 Z9 O1 ~/ l6 h9 B; Z
on page 50, }' w/ D; G4 o; n9 {# y1 _0 O
Removed# J# b, D) a6 X8 V' @
From Table 7, "Behavior for Reserved Multicast Addresses, on page 19; e4 c* P- q8 V1 X
0180C200-00-01
/ O% l, D! f+ [! { g0180-C2-00-00-10
6 ~( V9 s. W) O1 r5396-DS100-R 04/15/05 Initial release0 N5 Z3 E& ~; F$ }7 w
Broadcom Corporation$ v( j3 c. m$ Q* A
5300 California avenue; ]! }* [: ^7 o. K# G
Irvine, CA 926170 P4 ~3 c& M6 a' F
o 2013 by Broadcom Corporation
( c8 e7 N' ~" u$ _, C) dAll rights reserved
; h6 W3 q, z8 w7 W# FPrinted in the us.a
3 M) r, d! z6 hBroadcom, the pulse logo, Connecting everything, and the connecting everything logo are among the" s2 x+ U6 u/ |9 |3 n5 }# f
trademarks of Broadcom Corporation and/or its affiliates in the United States, certain other countries and or
* z, q" E( f) Y* n6 r' L, d! [the EU. Any other trademarks or trade names mentioned are the property of their respective owners3 B! ?3 P& I2 { L, @: {: g/ z, v
This data sheet ( including, without limitation, the broadcom component(s identified herein)is not designed,
3 y+ Y- k9 r/ ~' a( }intended, or certified for use in any military nuclear, medical, mass transportation aviation, navigations; q2 ~4 c+ z* g; C/ e& m
pollution control, hazardous substances management or other high-risk application BROADCOM PROVIDES" b. }8 L1 T9 K2 v/ o6 `! a
THIS DATA SHEET"AS-IS, WITHOUT WARRANTY OF ANY KIND. BROADCOM DISCLAIMS ALL WARRANTIES8 g& {: A v8 O t5 V; u
EXPRESSED AND IMPLIED, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF
1 x+ W+ l7 \9 a0 N7 k: \/ VMERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.# a# n7 u# h7 S! F8 @
0 P ]4 w# c1 O2 K. ?# |' y fBCM5396 Data Sheet; F: J4 `5 {) T/ z& n6 e+ I
Table of contents( _; P b. x& H+ s4 n- \
Table of contents
3 ^+ `. V! D& }+ U3 lAbout this document; k6 K! \- o# r7 d5 {
=·==·==·=·=·=. `. a9 u* Y4 A$ w# J4 h
24
2 m% C$ M, R2 oPurpose and audience; }6 y' @% [ `1 l9 A( t T
24
, G- u ]/ K; q4 XAcronyms and abbreviations4 x# ^ a. J2 {2 A0 }2 ^# y9 X
24# S! a& M% C* ?/ m/ U5 S& `
Document conventⅰonS∴
6 y" c1 X1 o: ]/ ] Y240 J. W) q# H: [: B7 ?* n( ^4 n) z' l
Technical Support.......
* z% k. @, ]7 ]·::·
0 K) \8 _/ o- Y$ L1 t( r24
( C. [" W6 k: R& y: F7 jSection 1: Introduction .minwoo 25
. G, v, R2 h( y I8 zOverview..…,,…
/ N2 q! I7 V! m( M* a/ O25' @: X8 n; E& ^ E! u2 p
Data Sheet Information
/ t; T/ ~0 z3 F+ F) W3 J0 ^25- p* J- {6 |; f) ]
Section 2: Features and operation .moon
1 d* g: H; d d! ~26$ W6 u0 @3 {- m
Overview.……
" g) {- N) T, V261 N- g5 G0 u: O; k8 a: F0 k
Quality of Service…
/ b# O& j, c9 V26
" T6 ^* S: g$ D( f0 JEgress transmit Queues..........................
; U, N6 \% W2 l# W: J! d6 r* Z6 j28
" \: ^7 J# w9 v; }/ S- FPort-Based Qos- U8 {1 I1 d/ C% J
28, M* I) O" \$ x( f9 ?+ W- _( _
IEEE Standard 802. 1P QoS. m6 C! C/ I5 `0 L* G" i
28
! ?& H' b6 m) Q5 u; ~( sMAC- Based Qos………….......7 U8 ?! s0 ^' t$ B" Z4 A( z
294 V0 D" W: c4 Z
DiffServ Qos… ~+ s' J) R: E. U, B
29) X- k0 k" L3 l3 ~/ i: e$ V
Ethertype Based Qos- b+ C5 u7 e7 s7 J- R2 P
29
. c }" D/ l1 `& n9 xFrame Priority Decision Tree
4 O' H1 a4 s- ^/ n0 F30
6 F/ z' H' R3 P- BPort- BasedⅥLAN,…………30& ]2 D) H- `0 a" N1 K1 U
lEEE Standard 802.1Q VLAN
( ?3 l: _7 i, }# q/ O4 J$ b311 l8 W, [: }3 M$ Y
VLAN Table organization……
t/ s+ V0 g, n: F31
3 i+ F) H! T7 e8 w: P% |: FProgramming the VLan table3 Q0 g4 k0 S% `
32
" W5 B5 Q$ O0 |; |; Y7 d; o& SJumbo frame Support. ....................................................................................................................33
. [2 D4 d: T0 S2 |Port Trunking/Aggregation- _, }/ z2 Q; G( M5 n+ O$ A
33+ a0 ]! p% E, p* D; U
Broadcast Storm Suppression/Rate Contro0 {7 w W+ A* [
··::··:···' b3 p/ N6 o* f8 t9 g% S7 S: X
348 B; {: D3 I# L- v
Two-Bucket System$ l z, P$ H3 r8 ^. |
35& V5 L$ E- I7 v6 N; C4 @
Bucket Bit Rate
- h( }) {) u R/ x2 h& `...I...................
8 o5 d. f9 m1 ^* H! d; o35
0 a! r/ U: o0 y1 ]1 BPort Mirroring+ I% B5 w+ Y1 q' y, g: k4 }
.36
# }) F; a6 C- Q% \; N* q; v: WEnabling Port mirroring……………,…,…,……
3 r- d2 B' w! d+ z% P6 I: K5 m% W" p6 W::.:a.:aa.:aa:::a
/ q0 A5 H* C& ~. @, Z3 q36
* s* x, i4 C1 V5 d; g- SCapture port
" f& ]9 [2 X4 P+ Y4 @9 `% k, t4 B36
+ M% Q _( v' G) D. C; J( hMirror Filtering rules...............* `- C& J! }# q1 Q7 [" V" r
37( y1 w) J8 `6 [$ V4 Y O7 `
Port mask filter
! ^- v2 Y5 Z$ g9 x, k.37
- ?5 x0 Q ~6 R5 `Packet divider filter.……
# N2 b3 n0 T& g∴379 d7 ^0 W& u) A }
IGMP Snooping, o. B; K% I4 F: D) h0 E
..:.a::a::.:
. ^! k$ a2 ^+ c9 V0 g! k0 c37) l4 W# u! \ G' E5 p- X
BROADCOMo
' ?/ G1 r* N6 y, NSingle-Chip 16-Port SerDes Gigabit Switch7 J0 [& U, N& E# E9 G
October4,2013·5396-DS114-R
6 C: G) s& R! z- f! J7 V5 }Page 7& c, ~; c L* j5 d, [, Z+ e+ d
BROADCOM CONFIDENTIAL' E d% X4 t) D9 |
r- T8 J8 q; `1 y; zBCM5396 Data Sheet
$ \; H3 ]/ Y7 L& r1 @( |Table of contents9 _" J0 w$ D+ Q: J
IP Layer IGMP Snooping………….…………………
7 W% A1 { d# x/ S; _38
W% O. H: q0 W- h# ~IEEE Standard 802. 1x Port-Based Security! d3 K8 J" w8 P2 U* y2 I0 i2 e
灬38 G1 S K E) _4 F- ~- J' ?$ E
Address Management$ w2 C v0 k4 X) ?
1..0 o1 @& m3 [9 [
39' s( _+ h; k' x. k! f$ m
Address Table Organization....,…,…,…,…,…
7 u* Y+ g- w( G& l% h392 M0 G0 Q: h+ Y; S
Address Learning..,..................' o' Z: k R L* a6 o, a) J0 ?$ r
···:a:::::a.··; X( _0 d# f' |" M! T( |3 b% Y
40( a( m2 q3 p4 E, b& L7 W( q
Address resolution and frame Forwarding. o# y) A5 X5 M5 r7 Q h% }6 z5 N& |
40/ ?4 C: y! j9 z f+ ]: s
Unicast Addresses
, u$ Q- I9 ?" }..40" P; C1 K7 t7 j# W- O7 ]4 H, k- f
Multicast Addresses.
7 z" ?% N7 S @' b. I3 kReserved multicast
\: `/ Y4 N3 |* @44; W% d$ I. q7 N8 S. V4 q Y
Using the Multiport Addresses…,,,…,…,…,,…,…,142 u1 e$ E+ x1 A
Static Address entrⅰes4 q. ] E0 e' g; B$ t
4
; m8 c6 Z, c" V- q5 `$ JAccessing the arl Table entries.......
+ b2 a2 c3 ?1 j1 Q: }2 P' H∴45
) q6 ~% ^1 k$ U5 Q: lReading an ARL Entry…
. J: z# M2 [! N1 {7 M45* G8 F7 b* \- F" l6 A+ G* s5 l
Writing an ARL Entry.……,…,…9 o* X# ?3 Q( h0 v
45" G [; z: O# T6 l' O
Searching the aRl table
5 Z) T. [8 o2 f# H+ A( O! O O46 t) J' u4 Z5 n- H& S8 ?+ I1 O
Address aging…....,.,,…,…,…
; J( n8 f: I* }- S' j46" S8 d' |6 v3 E! ~) }3 m
Fast Aging to Support Rapid Spanning Tree Protocol.
& F, [* J. v9 U( \Bridge management…. F! d3 t( b. Z
·自重自着重重
/ t6 T |2 n1 k( V* `2 x7 m/ f: x。(
' x4 }4 _# Z @7 i# P47
( y8 m0 V) I0 R3 n6 N# F% LSpanning Tree port state…….
" E. H) m- x% K$ W% N47$ H: y0 g: e4 p8 d5 V4 @
Disable
, ?/ _9 S7 G* ]( ^8 {48
) L8 H, o' t7 f6 R. Hblocking' Y" x2 q" i' c% e' H% `
48
. n! |/ m( ?7 R! X5 A7 UListening……,…,…,…,…,…
& [ q; n5 n5 q$ q( ~* |' W! Y48& q2 E/ \" o6 s4 e) M
Learning...…,,…,…,…,…,…,…………48
! d. Z7 R& l: O* ~! zForwarding.……
5 J& E! {- E4 ~9 H48
2 Q4 X$ ?; V- [, YManagement Frames.,.,…,…,…,…,…,…,…,,493 c6 _2 A% ]# l# D
Multiple Spanning tree Protocol (IEEE Standard 802. 1s)9 p9 s5 H; q% g. h7 y* w
50
' P" d# [! I) \2 ZSection 3: System Functional blocks
6 Z7 E9 [ `* Y/ n+ i7 @Overview, H8 h E$ O# i" U- l q0 `
酯·,8 @) y7 T7 _4 G( V( B. O2 F* h
.514 P& c2 U. ]( h9 ^, h$ u0 i
Media Access Controller.……2 Y! a5 W* b ?& ?3 F+ j: y
515 }# @, k! E$ K' o1 g" t7 n
Receive function.……51$ L7 v1 _2 W) {% q g' W }4 T' N
Transmit function
/ B3 b7 [+ J! P0 W/ V% @6 f: m% ?$ d.519 k; U9 K- `9 U
Flow Contro.…528 L2 A. f6 L, c0 n& b. X4 _
10/100 Mbps Half-Duplex Mode...............52) X7 {7 y& F) {% b$ [# ]) L+ p
10/100/1000 Mbps Full-Duplex Mode" c0 l$ X H5 U [0 ]6 q
52
1 o! ?; q+ o+ ?; hIntegrated High-Performance Memory9 K* c/ P" f$ |- A: f) h
52% u4 f1 r2 @2 C: \, Z- c
Switch Controller
+ \+ b% B$ [2 b0 c2 j53% z+ \1 }5 Z0 I, z
BROADCOMo+ h Q* b$ X- p
Single-Chip 16-Port SerDes Gigabit Switch
. d& ]2 U& ?6 P; o- ~4 E GOctober4,2013·5396-DS114-R
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BROADCOM CONFIDENTIAL' T' l" x! V8 z% x) a6 D" j; F9 v/ ^
+ p# J" Z7 m% j% ^+ sBCM5396 Data Sheet
5 m* E3 z0 [' @' i- y+ u; WTable of contents# V8 A) s7 [7 ]$ p; W' D+ l; U) ]6 p: O
Buffer Management……………………53/ m3 q5 Q" D% E
Memory arbitration................
. U! O6 N( |: |4 […53
$ I& Y* t; |4 ]6 ?9 j' e rTransmit Output Port Queues……3 n/ n% B! w0 a! ~
.53' U6 j5 s- L' F4 @- P8 X' V
Section 4: System Interfaces
: \+ ]2 {/ i" v5 n6 d5 y; e55
, V& ~1 h7 c7 a" MOverview
% p1 e1 N. r5 N( L3 m& z" s9 u9 L55/ J- ?! B4 g1 l% Q* J: M! y3 m
Serial| nterface∴
. L) k7 K5 n1 J* T% d B55& {, L& C5 b" u, l
SGMIl Mode
% h; G$ |9 G* @$ q i.552 K1 F' Q& f) J
SerDes mode,.wwwwwwwwwwwwwwwwwww56" S2 @$ i& \, L/ c" n- L6 x7 i
SerDes/sgML auto-Negotiation
$ I- Y. b8 `2 W% }; ^, D6! Q, Q1 G. U( o5 J
Frame Management9 @- F# w% {9 a6 @- z3 e
1··,音着自着1着着··自首,.自0 k6 \3 u1 q m1 `
56. u* N! ` T" s8 h% i' X$ D& e7 K/ W4 z
Reverse mll port) O- W$ W3 i" [- h/ `( W+ D
56
7 I" W4 B. K! [) i& i! BGMll Port5 _, Z& ^) ^- x1 q! ]( e5 ~! e
:a::::::::.::
. p1 ], R/ ]' a. d0 [::::::::·:::::::::·:·....;::::a:::::::a::.:::2 |2 @* h% o* Z9 R/ `1 ^ r( ~3 ^5 |
57& k* E4 M# J- I' R& P2 L( E
RGMI Port
4 j3 ]" V" n& n. D着D着·非·自·着·/ t) h1 c# ?; H; L+ ^8 ^+ {! n* Z a
.57
3 z/ L8 f8 H) @& u7 @In-Band Management Port ................................................................................................57
4 D# R* Z1 [ h) c4 f2 x0 AProgramming Interfaces....................................7 z7 w2 C/ P% b7 f
609 ]/ v3 R4 E% E* Q( x A
SP|| nterface.…
3 ]7 w) M) \* T: }9 \; M" m60
8 q6 G+ O. r7 }) A- jNormal spl mode
0 n- d+ U# Z' P8 U3 h1 x v62' `( B! m! r( L- M0 J4 i, P8 P
Fast sPl mode
0 `5 F0 E/ L( u; A& H& |0 d! Q65
Q% O7 ~" Y X4 h( _" c3 J0 F) u+ CEEPROM Interface..…,……………,……………………………………66
) x! _; @; L+ J9 U: p; U; sEEPROM Format
$ y2 _& p+ z% _/ S; z! j∴67; N7 V1 ^/ f* C: m
MDC/MDIO Interface.....................+ z9 T! j# Y( t/ U% j
68
; @3 l$ m8 S) N7 y. O6 DRegister Access Through Pseudo-PHY Interface- u2 }- F% J5 t/ f
:·:·:::.:..:·.·( j4 S' E7 @4 v4 y+ [
68
% P" F! |0 K( x% hMDC/MDIO Interface Register Programming
) I& m4 }/ v' D' ?4 {% L$ A72
% @1 O. q1 Y3 `. C) i3 d) d4 c8 ILED Interfaces6 q& G5 M/ P( ^; P
74
1 Y b0 }7 `( ?0 \/ RSerial led interface6 V% N8 z) _3 t: ]) _
74
3 r4 _$ [" k* ~, c2 f OSection5: Hardware Signal Definitions………,………………………77
z- V; R5 U; u9 P10 Signal Types.................
& M# P( f: {+ u6 y% a: y5 D' H T..:::::.::.:aaa::::a:::::a::::::- g% E0 c$ O; n" ]2 S" M
772 P% V/ ?2 ?' G7 J+ v) ~
Signal Descriptions
k7 |0 v. B" i2 i5 K78
& Y0 _) c; j: x7 A5 a; ^Section6: Pin Assignments…n…,…,…,…,……………84' m$ x+ o1 W \% o, x+ W
Section7: Register Definitions……,…,……,……,…,…,………89! U$ u* d. \- C8 |, z+ x/ M
Register Definition..................9 l7 y# ^, C1 B9 ~+ @8 W
89
* K* l, M# @) S2 s+ G. O, FControl Registers .....................................
' o8 s' @) P" b( p, {92
7 I: p* o; y8 i: p. p4 C! L# N10/100/1000 Port N Control Register [0: 15](Page oOh: Address 00h-OFh); ^3 |$ y: b! y4 k( _# O. |) x
94. r1 r' [4 j1 z% G
IMP Port(Port 16) Control Register(Page OOh: Address 10h).............94( |# L: h8 s/ Q. Y D& \
Switch Mode Register(Page ooh: Address 20h)) u* @" Z; h" h
95
' { Y; F9 f: B7 N5 @4 nBROADCOMo$ A. @! H( ^ l: ]# [4 N$ ~7 F2 k6 G; g
Single-Chip 16-Port SerDes Gigabit Switch
: I: N2 X) {, Q0 D }. zOctober4,2013·5396-DS114-R. v g. D7 }& G, d) R
Page 94 n! b! m2 Z& J; \0 s
BROADCOM CONFIDENTIAL
, D6 v$ R( J$ [) o( [: [
0 ^* d1 E4 V7 a: \; s' gBCM5396 Data Sheet5 e$ }6 [2 y7 `8 ]) z( @1 m
Table of contents
* G3 S, N% g8 y! b& yLED Control Register(Page oOh: Address 24h-25h)
6 j6 q6 w$ w5 l$ B/ G$ n1 ]" B$ S1 B.96
, C/ b, J: }& N5 Q" I1 \0 G9 zNew Control Register(Page ooh: Address 3Bh)
& J% V9 p L6 e& J∴96
M4 c$ i7 A' j% ?Reserved Multicast Control Register (Page ooh: Address 50h
! d9 D1 r( o' Z/ G/ ^97
/ A5 Q6 c5 @! e4 d- y @Load Meter Update Rate Control Register(Page00h: Address51h}………….….….….…974 X5 v1 a, F) \4 _( P6 _
Unicast Lookup Failed Forward Map register(Page 00h Addr 54h-57h).............98
0 t; Q' M& k- f' S( J8 n9 M; UMulticast Lookup Failed Forward Map register(Page 00h: Address 58h-5Bh)...........98
7 Z1 K( J7 B- EPort N State Override register[0: 15](Page oOh: Address 60h-6Fh)
& R0 u" f5 c6 R/ w z$ y1 H; v) L4 u98
) w2 R x* I$ l tPort 16(IMP) State Override Register(Page OOh: Address 70h)
! X! n: p, e# B5 N7 b7 a2 f99
( H( k* @, h9 w1 ]2 P802. 1X Control Register 1 (Page oOh: Address 77h)' J9 K' P# O3 R; y6 b
1007 R( z7 \, j6 y
802. 1X Control Register 2(Page oOh: Address 78h-7Bh)..........................100# Y; \* g) ~& n! J8 `1 b
SD DEFAULT Register(Page oOh: Address 80h-83h)+ g: l4 B' [8 ^& A( ] H8 K
100) U$ @$ I0 H3 ]2 r6 B6 Z [, y
SD SEL EARLY Register(Page 00h: Address 84h-85h).......................1014 L$ ?: S1 P; @8 {9 w
EXTERNAL PHY SCAN CONTROL Register
3 D0 d( V) w2 A4 |8 {! `Fast Aging Control Register(Page ooh: Address 88h)3 H/ U; k: E! S J6 M, l4 X
102
6 d% b7 V' U5 v& i4 _Fast Aging Port Register(Page OOh: Address 89h)- l s5 G Z" K4 M: q+ p
1028 C" ~* g) Z1 c5 i
Fast Aging VID Register( Page C0h: Address8Ah-8Bh),,,…………………102. C1 l( N4 [6 {: ]0 } V8 p0 m5 F7 C
Pause Frame Detection Control Register(Page 00h: Address 90h).................1033 L$ o" P8 ?; L0 _
Status Registe g. }) P* d; A) u
104
5 o+ t* I9 C$ ], l0 Z* HLink Status Summary( Page O1h: Address00h-03h)…….….……………………………………105
. t o6 w. S6 Y+ _, PLink Status Change(Page 01h: Address 04h-07h)........................1057 O0 W$ H, C6 S. R! ~" L$ o5 f! }
Port Speed Summary (page 01h: Address 08h-oFh).........................105" d, {2 C( T3 N/ e! |# U B
Duplex Status Summary( Page o1h: Address 10h-13h)
6 ^) I; l8 |7 \4 `* e' v/ ^ j.106
8 ^( `1 X* e9 b$ F6 c+ rTX Pause Status Summary(Page 01h: Address 14h-17h
0 Q) f) ]; l M% ~) L" b) i, w* A106
& O9 l6 Y4 M; h1 wRX Pause Status Summary(Page 01h: Address 18h-1Bh/ f6 P- V5 ~$ f! S
a.::.::.::' V5 }4 ]$ e7 H3 Q* S* ~4 R% F
106
% @- j6 Q& n; b, hPort N PHY Status Register[0: 15](Page 01h: Address 20h-2Fh)..........................107 A) R: E: P/ [
SerDes signal Detect Status Register (Page 01h: Address 40h- h! N7 C0 M N+ q/ _) E
107; h& D+ G! l% z. K6 p( Q. Y' L
BIsT Status Register(Page01h, Address45h)....,.,.,.,,…,…,…,…,………,107
2 b- Q' X3 G8 l d# Q5 G1 W6 @Strap value register(Page 01h: Address 70h-73h).................................108 \( M! d j: f0 F0 W2 ?0 ~
Management Mode registers. F4 O; w; K) x
,………,1095 A) [$ p3 N/ K" r" E% Q! v- z
Global Management Configuration Register
4 I$ _# k% r! {4 V2 A" e; c* O+ D, t109% Y: ], |& Y+ c7 P8 q
Aging Time Control(Page02h: Address och-0Fh).,,,,…,………………110
% A; I9 N( g' S, n- m8 A& birror Capture Control Register(Page 02h: Address 10h-11h
. g( \! m& o5 p2 I3 u10( {& E( l. U" |8 ?0 q
Ingress Mirror Control Register (Page 02h: Address 12h-15h)...................111
9 a, K* M4 D& w* Y: tIngress Mirror Divider(Page 02h: Address 16h-17h) z! I$ k7 T9 X$ u) u1 O
111
. e; L% |$ k+ R: R2 I% bEgress Mirror contro| Register(Page02h: Address1Ch-1Fh).……………………,112* O7 {: |1 F" P/ p) ~9 r; ~( b
Model ID(Page 02h: Address 30h+ M1 N- _! K* d# j9 e
112
\) y9 E( _/ u, C% tBROADCOMo m. G& V/ t& F" g/ R4 _( p! Q0 ?
Single-Chip 16-Port SerDes Gigabit Switch! P+ A1 Z( Q1 K0 D
October4,2013·5396-DS114-R; s. L% Q5 X& n& U5 b9 P
Page 10
" m( h9 Y1 K8 H) D/ t. P9 H' j; TBROADCOM CONFIDENTIAL
4 k4 |: Y* a/ o. N" o( }% c: T+ M# P: P9 a0 U5 U
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