16口千兆交换机芯片BCM5396 Data Sheet 数据手册
Single-Chip 16-Port SerDes Gigabit Switch16-port 10/100/1000 Mbps integrated switch
controller via 1.25G SerDes/SGMII/fiber
• Embedded 256 KB on-chip packet buffer
• One 10/100/1000 Mbps In-band Management
Port (IMP) with GMII/RGMII/RvMII/MII interface
for PHY-less connection to a CPU/management
entity (for management purposes only)
• Integrated address management
• Supports up to 4K MAC addresses
• Supports jumbo frames up to 9728 bytes.
• Supports EEPROM for low-cost chip configuration
• Integrated Motorola® SPI-compatible interface
• Supports port mirroring
• Port-based VLAN and 4K IEEE 802.1Q tag VLAN
• Port-, DiffServ-, MAC-, and IEEE 802.1p-based QoS
for four queues
• Supports Spanning Tree, Rapid Spanning Tree, and
Multiple Spanning Tree protocols (802.1D/1s/1w)
• Supports IEEE Standard 802.1X port security
• Supports pseudo-PHY MDIO access
• MAC-based trunking with link fail-over
• Ethernet-in-the-last-mile (EFM) support: OAM and
P
• Low-power (2.2W total) 1.2V core/2.5V (SGMII I/
O)/3.3V (GMII/MII/RvMII) and 2.5V RGMII
operation with 3.3V I/O tolerance
• 256-pin FBGA package
BCM5396 Data sheet
Revision History
Revision History
Revision
Date
Change description
5396-DS114-R10/4/13 Added
"ethertype based qos on page 29
Updated:
Figure 2: Priority packet Mapping Flow, on page 27
Table 1: Frame Priority Decision Tree Summary on page 30
·“ Jumbo frame Support" on page33
Table 17: Pseudo-PHY Mll Register Definitions on page 72
Serial LED Interface"on page 74
Table 43: External PHY Scan Control Register(Page oOh: Address 86h)
on page 101
Table 177: Serial lEd Interface Timing, on page 191
5396-DS113-R 02/07/12 Updated
Table 139: Internal Ser Des registers Page descriptions 10h-1Fh, " on
page 145
Table 140: " Internal Ser Des Registers Page 10h-1Fh on page 145
Table 192: New Priority Map Register(Pages 34h: Address oC-OFh,on
page 185
5396-DS112R06/10/10 Updated:
Table 144: Auto-Negotiation Link Partner ability (page 10h-1Fh
Address 0Ah-OBh), on page 153
PRBS Status Register(Page 10h"1Fh: Address 32h" 33h)"on page 166.
5396-Ds111R08/2609 Updated:
Section 12: Ordering Information, on page 175
5396-DS110R02/2508 Updated:
Signal descriptions on page 54: BIST CLRMEM SEL and SKIP MEMbIS
descriptions
Removed
References to behavior of management frames in unmanaged mode
5396-DS109R11/13/07 Updated
Management Frames" on page 24, and"Frame Management on
page 32: Corrected terminology relating to the in-band management
port
Table 59, Management Mode registers (Page 02h), on page 81:
Changed definition of bits 7: 6
Added:
In-Band Management port"on page 33 Added note
Table 23, Signal Descriptions, on page 53 and "Pin Assignments"on
page 58: Added BIST CLRMEM SEL, SKIPMEMBIST, EN EXT CLK, and
EXT CLK signals to all signal/pin tables and figures
BROADCOMe
Single-Chip 16-Port SerDes Gigabit Switch
October4,2013·5396-DS114-R
Page 3
BROADCOM CONFIDENTIAL
BCM5396 Data sheet
Revision History
Revision
Date
Change description
5396-Ds108R06/2507 Updated:
In-Band Management Port"on page 33
Table 28, 10/100/1000 Port Control Register(Page o0h: Address 00h-
OFh),on page 69
Table 29, "IMP Port Control Register(Page 00h: Address 10h), on page
69.
Table 66, Global Management Configuration Register(Page 02h
Address ooh), on page 86
Table 229, Thermal Properties with External heat sink 23 mm. 23 mm
15 mm. Blade Fin, on page 180
Removed
Memory Test Control Register Page 00h: Address EOh) from page 75
5395DS107-R07/126 Updated:
Figure 39, 256-Pin FBGA Package Outline Drawing, on page 181
5396-DS106-R05/2406Aded:
Table 154, BER/CRC Error Counter Register(Page 10h" 1Fh: Address 2Eh
2Fh),on page 128
Table 155, PRBS Control Register(Page 10h"1Fh: Address 30h "31h)
page 128
Table 156, PRBS Control Register(Page 10h" 1Fh: Address 32h" 33h),
on page 128
Table 157, Pattern Generator Control Register( Page 10h 1Fh: Address
34h"35h),on page 129
Table 158, Pattern Generator Control Register(Page 10h 1Fh: Address
36h" 37h), on page 130
Table 159, Pattern Generator Control Register(Page 10h" 1Fh: Address
36h~37h)," on page130.
Table 160, Force Transmit 1 Register(Page 10h" 1Fh: Address 3Ah
3Bh),on page 130
Table 161, Block Address(Pages 10h-1Fh: Address 3Eh"3Fh),on page
131
BROADCOMe
Single-Chip 16-Port SerDes Gigabit Switch
October4,2013·5396-DS114-R
Page 4
BROADCOM CONFIDENTIAL
BCM5396 Data sheet
Revision History
Revision
Date
Change description
5396-DS105R0419/06 Updated:
Features list on front cover
."LED Interfaces" on page 50
Table 23, "Signal Descriptions on page 53
Table 24, "Pin Assignment(Listed by pin Number) on page 58
Table 25, "Pin Assignment ( Listed by Signal Name), on page 60
· Figure21,“ Pins Top view," on page62.
Table 27, "Control Registers(Page ooh),"on page 67.
LED A, B, C, and d registers to reserved in Table 27, Control registers
(Page ooh), on page 67
Table 65, Strap value Register(Page 01h: Address 70h-73h), " on page
85
Table 94, " ARL Search Result Register(Page 05h: Address 3Bh-3Eh), on
page 98
Table 95,"ARL Search MAC/VID Result Register 1(Page 05h: Address
40h-47h) , on page 98
Table 231," Ordering Information on page 182
Removed
LED A, B, C, and d register descriptions from section"Control registers
on page 67.
5396-DS104R11/10/05Aded:
I-temp package ordering information to Table 223,"Ordering
Information
5396-DS103-R 09/21/05 Updated
The minimum, typical, and maximum for the 2.5v power rail pin in table
208, "Electrical characteristics
5396Ds102R09/1605 Updated:
The minimum, typical, maximum, and units for the 2. 5v power rail pin in
Table 208, Electrical Characteristics
Added:
3. 3V power rail (IMP port) pin for IDD symbol in Table 208,"Electrical
Characteristics"8
BROADCOMe
Single-Chip 16-Port SerDes Gigabit Switch
October4,2013·5396-DS114-R
Page 5
BROADCOM CONFIDENTIAL
Revision
Date
Change Description
5396-DS101-R 09/13/05 Updated
Figure 16, Serial EEPROM Connection, on page 42
That the aUto Poll DiS pin is pulled low,
reset in"MDC/MDIO Interface"on page 4 hot high, during power-on/
Figure 17, MDC/MDIO Interface, on page 44
When the switch is master-sourcing to When the switch is slave-driven in
MDC/MDIO Interface Register Programming"on page 49
In Table 23, Signal Descriptions on page 53
Description for hw fWdG EN
Type for EXTCLK
Pages 50h-60h to Reserved in Table 26, Global Page Register Map on
age 64
The Description in Table 95, ARL Search Control register(Page 05h
Address 30h),on page 98
The default in Table 169, "Queue N Weight Register(Page 30h: Address
81h-84h), "on page 132
Table 208, Electrical Characteristics, on page 158
Added
Page 00 Addr 24H"25H Bit to Table 19, "Serial LED Mode matrix
on page 50
Removed
From Table 7, "Behavior for Reserved Multicast Addresses, on page 19
0180C200-00-01
0180-C2-00-00-10
5396-DS100-R 04/15/05 Initial release
Broadcom Corporation
5300 California avenue
Irvine, CA 92617
o 2013 by Broadcom Corporation
All rights reserved
Printed in the us.a
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intended, or certified for use in any military nuclear, medical, mass transportation aviation, navigations
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THIS DATA SHEET"AS-IS, WITHOUT WARRANTY OF ANY KIND. BROADCOM DISCLAIMS ALL WARRANTIES
EXPRESSED AND IMPLIED, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF
MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
BCM5396 Data Sheet
Table of contents
Table of contents
About this document
=·==·==·=·=·=
24
Purpose and audience
24
Acronyms and abbreviations
24
Document conventⅰonS∴
24
Technical Support.......
·::·
24
Section 1: Introduction .minwoo 25
Overview..…,,…
25
Data Sheet Information
25
Section 2: Features and operation .moon
26
Overview.……
26
Quality of Service…
26
Egress transmit Queues..........................
28
Port-Based Qos
28
IEEE Standard 802. 1P QoS
28
MAC- Based Qos………….......
29
DiffServ Qos…
29
Ethertype Based Qos
29
Frame Priority Decision Tree
30
Port- BasedⅥLAN,…………30
lEEE Standard 802.1Q VLAN
31
VLAN Table organization……
31
Programming the VLan table
32
Jumbo frame Support. ....................................................................................................................33
Port Trunking/Aggregation
33
Broadcast Storm Suppression/Rate Contro
··::··:···
34
Two-Bucket System
35
Bucket Bit Rate
...I...................
35
Port Mirroring
.36
Enabling Port mirroring……………,…,…,……
::.:a.:aa.:aa:::a
36
Capture port
36
Mirror Filtering rules...............
37
Port mask filter
.37
Packet divider filter.……
∴37
IGMP Snooping
..:.a::a::.:
37
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BROADCOM CONFIDENTIAL
BCM5396 Data Sheet
Table of contents
IP Layer IGMP Snooping………….…………………
38
IEEE Standard 802. 1x Port-Based Security
灬38
Address Management
1..
39
Address Table Organization....,…,…,…,…,…
39
Address Learning..,..................
···:a:::::a.··
40
Address resolution and frame Forwarding
40
Unicast Addresses
..40
Multicast Addresses.
Reserved multicast
44
Using the Multiport Addresses…,,,…,…,…,,…,…,14
Static Address entrⅰes
4
Accessing the arl Table entries.......
∴45
Reading an ARL Entry…
45
Writing an ARL Entry.……,…,…
45
Searching the aRl table
46
Address aging…....,.,,…,…,…
46
Fast Aging to Support Rapid Spanning Tree Protocol.
Bridge management…
·自重自着重重
。(
47
Spanning Tree port state…….
47
Disable
48
blocking
48
Listening……,…,…,…,…,…
48
Learning...…,,…,…,…,…,…,…………48
Forwarding.……
48
Management Frames.,.,…,…,…,…,…,…,…,,49
Multiple Spanning tree Protocol (IEEE Standard 802. 1s)
50
Section 3: System Functional blocks
Overview
酯·,
.51
Media Access Controller.……
51
Receive function.……51
Transmit function
.51
Flow Contro.…52
10/100 Mbps Half-Duplex Mode...............52
10/100/1000 Mbps Full-Duplex Mode
52
Integrated High-Performance Memory
52
Switch Controller
53
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BCM5396 Data Sheet
Table of contents
Buffer Management……………………53
Memory arbitration................
…53
Transmit Output Port Queues……
.53
Section 4: System Interfaces
55
Overview
55
Serial| nterface∴
55
SGMIl Mode
.55
SerDes mode,.wwwwwwwwwwwwwwwwwww56
SerDes/sgML auto-Negotiation
6
Frame Management
1··,音着自着1着着··自首,.自
56
Reverse mll port
56
GMll Port
:a::::::::.::
::::::::·:::::::::·:·....;::::a:::::::a::.:::
57
RGMI Port
着D着·非·自·着·
.57
In-Band Management Port ................................................................................................57
Programming Interfaces....................................
60
SP|| nterface.…
60
Normal spl mode
62
Fast sPl mode
65
EEPROM Interface..…,……………,……………………………………66
EEPROM Format
∴67
MDC/MDIO Interface.....................
68
Register Access Through Pseudo-PHY Interface
:·:·:::.:..:·.·
68
MDC/MDIO Interface Register Programming
72
LED Interfaces
74
Serial led interface
74
Section5: Hardware Signal Definitions………,………………………77
10 Signal Types.................
..:::::.::.:aaa::::a:::::a::::::
77
Signal Descriptions
78
Section6: Pin Assignments…n…,…,…,…,……………84
Section7: Register Definitions……,…,……,……,…,…,………89
Register Definition..................
89
Control Registers .....................................
92
10/100/1000 Port N Control Register (Page oOh: Address 00h-OFh)
94
IMP Port(Port 16) Control Register(Page OOh: Address 10h).............94
Switch Mode Register(Page ooh: Address 20h)
95
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BROADCOM CONFIDENTIAL
BCM5396 Data Sheet
Table of contents
LED Control Register(Page oOh: Address 24h-25h)
.96
New Control Register(Page ooh: Address 3Bh)
∴96
Reserved Multicast Control Register (Page ooh: Address 50h
97
Load Meter Update Rate Control Register(Page00h: Address51h}………….….….….…97
Unicast Lookup Failed Forward Map register(Page 00h Addr 54h-57h).............98
Multicast Lookup Failed Forward Map register(Page 00h: Address 58h-5Bh)...........98
Port N State Override register(Page oOh: Address 60h-6Fh)
98
Port 16(IMP) State Override Register(Page OOh: Address 70h)
99
802. 1X Control Register 1 (Page oOh: Address 77h)
100
802. 1X Control Register 2(Page oOh: Address 78h-7Bh)..........................100
SD DEFAULT Register(Page oOh: Address 80h-83h)
100
SD SEL EARLY Register(Page 00h: Address 84h-85h).......................101
EXTERNAL PHY SCAN CONTROL Register
Fast Aging Control Register(Page ooh: Address 88h)
102
Fast Aging Port Register(Page OOh: Address 89h)
102
Fast Aging VID Register( Page C0h: Address8Ah-8Bh),,,…………………102
Pause Frame Detection Control Register(Page 00h: Address 90h).................103
Status Registe
104
Link Status Summary( Page O1h: Address00h-03h)…….….……………………………………105
Link Status Change(Page 01h: Address 04h-07h)........................105
Port Speed Summary (page 01h: Address 08h-oFh).........................105
Duplex Status Summary( Page o1h: Address 10h-13h)
.106
TX Pause Status Summary(Page 01h: Address 14h-17h
106
RX Pause Status Summary(Page 01h: Address 18h-1Bh
a.::.::.::
106
Port N PHY Status Register(Page 01h: Address 20h-2Fh)..........................107
SerDes signal Detect Status Register (Page 01h: Address 40h
107
BIsT Status Register(Page01h, Address45h)....,.,.,.,,…,…,…,…,………,107
Strap value register(Page 01h: Address 70h-73h).................................108
Management Mode registers
,………,109
Global Management Configuration Register
109
Aging Time Control(Page02h: Address och-0Fh).,,,,…,………………110
irror Capture Control Register(Page 02h: Address 10h-11h
10
Ingress Mirror Control Register (Page 02h: Address 12h-15h)...................111
Ingress Mirror Divider(Page 02h: Address 16h-17h)
111
Egress Mirror contro| Register(Page02h: Address1Ch-1Fh).……………………,112
Model ID(Page 02h: Address 30h
112
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